#create_ccopt_clock_tree_spec -file RPT/cts/ccopt.spec
#source RPT/cts/ccopt.spec
#example
#modify_ccopt_skew_group -skew_group clkA/func -remove_sinks {pin1 pin2 }
#modify_ccopt_skew_group -skew_group clkA/func -add_sinks {pin1 pin2 }
#delete_ccopt_skew_groups clkA/func
#create_ccopt_skew_group -name clk_group_blance1 -balance_skew_groups {clkB/func clkC/func}
set_ccopt_property target_skew 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/ucpu0/ck_gclkt insertion_delay 0.80
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/ucpu1/ck_gclkt insertion_delay 0.80
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/ucpu2/ck_gclkt insertion_delay 0.80
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/ucpu3/ck_gclkt insertion_delay 0.80
create_ccopt_skew_group -name crm_pll_test_wrapper_pll_dft_div/inst_cbb_clk_gate_clk1 \
-source inst_cpu_crm/inst_pll/PLLOUT1 \
-sink { \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div2/genblk1_inst_clkout_dff/inst_SDFCNQD4BWP6T16P96CPD/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div4/genblk1_cnt_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div4/genblk1_inst_clkout_dff/inst_SDFCNQD4BWP6T16P96CPD/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div8/genblk1_cnt_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div8/genblk1_cnt_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div8/genblk1_inst_clkout_dff/inst_SDFCNQD4BWP6T16P96CPD/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_freq_check/clk_gate_pll_clk_freq_cnt_reg/latch/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_6/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_4/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_3/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_1/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_2/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_0/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_counter_reg_5/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/div_clk_en_reg_0/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/pll_div_0_inst_cbb_sync_stage2_rst_clk/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/pll_div_0_inst_cbb_sync_stage2_rst_clk/inst_SDFSYNCNQD2BWP6T16P96CPD_stage1/CP \
} \
-rank 1
create_ccopt_skew_group -name plla_clk_div2_genblk1_inst_clkout_dff \
-source inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/inst_plla_clk_div2/genblk1_inst_clkout_dff/inst_SDFCNQD4BWP6T16P96CPD/Q \
-sink { \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/sel_clk2_d4_reg/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst2_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst2_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst2_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk2_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk2_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk2_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
} \
-rank 1
# inst_cpu_crm/inst_cpu_lcgu/inst_cpu_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/E -0.9
create_ccopt_skew_group -name crm_lcgu_cpu_clk_cg_cbb_clk_gate_A1 \
-source inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst8_clk_gate/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/Q \
-sink { \
inst_cpu_crm/inst_cpu_lcgu/cpu_atb_clk_en_d_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/cpu_atb_clk_en_d_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_atb_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_atb_clk_div_sel_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_atb_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/sync_scanen_2nd_reg_reg/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/sync_scanen_1st_reg_reg/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_gic_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_gic_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_gic_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_cnt_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_cnt_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_cnt_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_atb_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_atb_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_atb_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_acp_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_acp_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_acp_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_ace_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_ace_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_ace_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_clk_en_sync/inst_SDFSYNSNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_4/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_5/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_6/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/div_cnt_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_mclk_cpu_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_mclk_cpu_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_mclk_cpu_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_gic_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_gic_clk_div_sel_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_gic_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_cnt_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_cnt_clk_div_sel_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_cnt_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_acp_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_acp_clk_div_sel_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_acp_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_clk_div_sel_reg_1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_ace_clk_div_sel_reg_0/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_ace_clk_div_sel_reg_2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/cpu_ace_clk_div_sel_reg_1/CP \
} \
-rank 1
#endpoint: inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_fast_clk_inst/U_fast_clk_latch/inst_CKLNQCTD12BWP6T16P96CPD/E -0.795
create_ccopt_skew_group -name crm_cbb_dft_occ_cpu_clk_cbb_dft_fast_clk_fast_clk_latch \
-source inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/inst_scan_clk_mux/inst_CKMUX2D4BWP6T16P96CPD/Z \
-sink { \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_scan_out_reg/EN \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_clock_pulse_en_reg_reg_0/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_clock_pulse_en_reg_reg_1/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_clock_pulse_en_reg_reg_2/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_clock_pulse_en_reg_reg_3/CP \
inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_clk_pulse_inst/dft_clock_pulse_en_reg_reg_4/CP } \
-rank 1
# set_ccopt_property -pin inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/U_delay_clock_latch/inst_CKLNQCTD12BWP6T16P96CPD/CP insertion_delay 0.500
#set ICG1
create_ccopt_skew_group -name ICG1 \
-source inst_cpu_crm/inst_cpu_lcgu/inst_plla_fixed_divider/U3/Z \
-sink {\
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/sel_clk1_d4_reg/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst1_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst1_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst1_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk1_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk1_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk1_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
} \
-rank 1
#set ICG2
create_ccopt_skew_group -name ICG2 \
-source inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/U38/ZN \
-sink { \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst_cbb_sync_stage3_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst_cbb_sync_stage3_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst_cbb_sync_stage3_rst_sync/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst8_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage3/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst8_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stage2/CP \
inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst8_cbb_sync_stage3_rst/inst_SDFSYNCNQD2BWP6T16P96CPD_stag1/CP \
} \
-rank 1
#from inst8
# CKLNQCTD12BWP6T16P96CPD 1411.71 587.86 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_gic_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# CKLNQCTD12BWP6T16P96CPD 1406.91 573.55 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_cnt_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# CKLNQCTD12BWP6T16P96CPD 1404.99 575.09 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_atb_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# CKLNQCTD12BWP6T16P96CPD 1404.61 573.26 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_acp_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# CKLNQCTD12BWP6T16P96CPD 1405.18 572.78 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_ace_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# CKLNQCTD12BWP6T16P96CPD 1406.18 597.36 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_clk_cg/inst_CKLNQCTD12BWP6T16P96CPD/CP
# from IO
# CKLNQD1BWP6T16P96CPD 1406.24 541.78 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_gic_clk_div_sel_reg/latch/CP
# CKLNQD1BWP6T16P96CPD 1407.01 544.08 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_cnt_clk_div_sel_reg/latch/CP
# CKLNQD1BWP6T16P96CPD 1417.79 537.94 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_atb_clk_div_sel_reg/latch/CP
# CKLNQD1BWP6T16P96CPD 1413.95 537.46 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_acp_clk_div_sel_reg/latch/CP
# CKLNQD1BWP6T16P96CPD 1419.49 537.46 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_ace_clk_div_sel_reg/latch/CP
# CKLNQD1BWP6T16P96CPD 1407.01 545.62 inst_cpu_crm/inst_cpu_lcgu/inst_cpu_sel_div/clk_gate_cpu_clk_div_sel_reg/latch/CP
#from U3
#inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst1_clk_gate/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/CP
#from U38
#inst_cpu_crm/inst_cpu_lcgu/inst_cpu_dtcm/inst_clk_mux/inst8_clk_gate/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/CP
#from PLLOUT
#inst_cpu_crm/inst_pll_test_wrapper/inst_pll_freq_check/clk_gate_pll_clk_freq_cnt_reg/latch/CP
#inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/pll_div_0_inst_cbb_clk_gate_clk/inst_CKLNQCTD12BWP6T16P96CPD/CP
# inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/inst_cbb_clk_gate_delay_clk/inst_CKLNQCTD12BWP6T16P96CPD/E (-0.656)
#set_ccopt_property -pin inst_cpu_crm/inst_cbb_dft_occ_cpu_clk/U_cbb_dft_scanen_sync_inst/sync_scanen_2nd_reg_reg/CP insertion_delay 0.400
#inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/uck_gclkb0/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/ck_l2_tbnk0_clk_en_dly_q_reg/CP insertion_delay 0.3
# inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/uck_gclkb1/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/ck_l2_tbnk1_clk_en_dly_q_reg/CP insertion_delay 0.3
# inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/uck_gclkl2/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/ck_l2_logic_clk_en_dly_q_reg/CP insertion_delay 0.2
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/clk_gate_l2_tbnk_wr_fail_hazchk_feq_l4_q_reg/latch/E -0.35
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_tbnk_vld_l3_q_reg/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_tbnk_vld_l3_q_reg/CP insertion_delay 0.15
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_tbnk_sel_l3_q_reg_0/CP insertion_delay 0.15
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_tbnk_all_b2_reg/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_data1_sel_b2_reg/CP insertion_delay 0.15
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_data0_sel_b2_reg/CP insertion_delay 0.15
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_data3_sel_b2_reg/CP insertion_delay 0.15
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utag_pipe/l2_mbist2_data2_sel_b2_reg/CP insertion_delay 0.15
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/clk_gate_l2_tbnk0_cpu2_wr_byp_on_rr_cnt_q_reg/latch/E -0.31
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_cpu0_rd_addr_arb_q_reg_6/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_cpu1_rd_addr_arb_q_reg_6/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_cpu2_rd_addr_arb_q_reg_6/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_cpu3_rd_addr_arb_q_reg_6/CP insertion_delay 0.1
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu3_logic/ucpu_logic_tbnk0/clk_gate_l2_tbnk_snp_tag_single_ecc_err_l4_q_reg/latch/E -0.304
# inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/usb_ctl2/uck_gclksb/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_b2/u_full_bridge/fifo_full_reg/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a2/u_full_bridge/valid_dst_reg_reg/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_b2/u_full_bridge/valid_dst_reg_reg/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a2/u_full_bridge/fifo_full_reg/CP insertion_delay 0.05
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/usb_ctl3/uck_gclksb/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_b3/u_full_bridge/fifo_full_reg/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/valid_dst_reg_reg/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/rd_ptr_reg_0/CP insertion_delay 0.06
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/wr_ptr_reg_0/CP insertion_delay 0.06
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/fifo_full_reg/CP insertion_delay 0.06
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/rd_ptr_reg_1/CP insertion_delay 0.06
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a3/u_full_bridge/wr_ptr_reg_1/CP insertion_delay 0.06
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/uck_gclkl2_b0/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/ck_l2_feq_tbnk0_clk_en_dly_q_reg/CP insertion_delay 0.1
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/usram_l2_tbnk1_snp_3/clk_gate_data_in_mod_reg_0/latch/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_ccb_change_state_l1_q_reg_3/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_ls_xfer_l1_q_reg_3/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_dbe_l1_q_reg/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_type_l1_q_reg_2/CP insertion_delay 0.03
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_type_l1_q_reg_1/CP insertion_delay 0.03
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_type_l1_q_reg_0/CP insertion_delay 0.03
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_type_l1_q_reg_2/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_type_l1_q_reg_0/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_type_l1_q_reg_1/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_addr_l1_q_reg_1/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_owner_l1_q_reg_1/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_owner_l1_q_reg_0/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_owner_l1_q_reg_2/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_addr_l1_q_reg_2/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_addr_l1_q_reg_3/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_wr_err_l1_q_reg/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_vld_l1_q_reg/CP insertion_delay 0.03
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/usb_ctl0/uck_gclksb/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_b0/u_full_bridge/fifo_full_reg/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/valid_dst_reg_reg/CP insertion_delay 0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/rd_ptr_reg_0/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/wr_ptr_reg_0/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/fifo_full_reg/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/rd_ptr_reg_1/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/udt_sb/ucxatbsyncbridge_32b_maia_a0/u_full_bridge/wr_ptr_reg_1/CP insertion_delay 0.05
# need add delay to inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/clk_gate_l2_dvmcomp_resp_count_q_reg/latch/E CP 0.1
# need add delay to inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_abf/clk_gate_l2_feq_axi_read_addr_arb_q_reg_0/latch/E CP 0.1
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu2_logic/ucpu_logic_tbnk0/clk_gate_l2_tbnk_snp_tag_single_ecc_err_l4_q_reg/latch/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu2_logic/ucpu_logic_tbnk0/l2_tbnk_snp_rd_acc_l3_q_reg/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu2_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_1/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu2_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_0/CP insertion_delay 0.1
# inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu1_logic/ucpu_logic_tbnk0/clk_gate_l2_tbnk_snp_tag_single_ecc_err_l4_q_reg/latch/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu1_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_0/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu1_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_1/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu1_logic/ucpu_logic_tbnk0/l2_tbnk_snp_rd_acc_l3_q_reg/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_0/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_1/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_tbnk0/l2_tbnk_snp_rd_acc_l3_q_reg/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu3_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_0/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu3_logic/ucpu_logic_tbnk0/l2_tbnk_ecc_rmw_rd_l3_q_reg_1/CP insertion_delay 0.1
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu3_logic/ucpu_logic_tbnk0/l2_tbnk_snp_rd_acc_l3_q_reg/CP insertion_delay 0.1
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/usram_l2_tbnk1_snp_2/clk_gate_data_in_mod_reg_0/latch/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_ccb_change_state_l1_q_reg_2/CP insertion_delay 0.08
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk1_rwvic_ls_xfer_l1_q_reg_2/CP insertion_delay 0.05
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utbnk_mbist/cpu_subsys_top_rtl_tessent_mbist_c2_shared_bus_assembly_inst/cpu_subsys_top_rtl_tessent_mbist_c2_shared_bus_glue_logic_inst/tessent_persistent_cell_GATING_BIST_CLK/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk0/utbnk_mbist/cpu_subsys_top_rtl_tessent_mbist_c2_shared_bus_assembly_inst/cpu_subsys_top_rtl_tessent_mbist_c2_controller_inst/BIST_CLK_EN_RETIME2_reg/CP insertion_delay 0.08
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/clk_gate_l2_tbnk0_cpu0_wr_byp_on_rr_cnt_q_reg/latch/E
#check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_dbf/clk_gate_l2_feq16_rdb0_qw_en_q_reg/latch/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_rdb1_barrier_resp_q_reg/CP insertion_delay 0.08
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_7/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_5/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_3/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_cmo_q_reg_26/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_cmo_q_reg_25/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_cmo_q_reg_27/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_9/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_11/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_15/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_feq_rdb1_wa_stream_q_reg_13/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/l2_rdb1_to_feq_dec_q_reg_18/CP insertion_delay 0.05
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk1/utag_pipe/clk_gate_l2_tbnk_incl_plru_wren_l2_q_reg/latch/E
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uspr_aon3/clk_gate_ic_spr_rd_data_q_reg_2/latch/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_5/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_6/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_8/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_1/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_7/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_2/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_0/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_rd_q_reg/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_4/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uic/uaon3/sr_addr_q_reg_3/CP insertion_delay 0.05
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/uck_gclkl2_b1/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ufeq_ctl/ck_l2_feq_tbnk1_clk_en_dly_q_reg/CP insertion_delay 0.08
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/clk_gate_l2_ctlr0_q_reg/latch/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_5/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_1/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_0/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_4/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_2/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_6/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_8/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_7/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu1_l2_spr_addr_q_reg_3/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_0/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_1/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_5/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_6/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_8/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_4/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_3/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_2/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/ds_cpu0_l2_spr_addr_q_reg_7/CP insertion_delay 0.05
#check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/usram_l2_tbnk0_snp_1/clk_gate_data_in_mod_reg_3/latch/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk0_rwvic_type_l1_q_reg_2/CP insertion_delay 0.05
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_tbnk0_rwvic_type_l1_q_reg_1/CP insertion_delay 0.05
# check_fanin_reg inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/clk_gate_l2_cpu_tocpu1_peq_snp_haz_clr_q_reg/latch/E
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_tbnk0_snp_rd_acc_l4_dly_q_reg/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_tbnk0_snp_data_vld_l4_dly_q_reg/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_tbnk1_wbna_l4_dly_q_reg/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_6/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_8/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_9/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_4/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_7/CP insertion_delay 0.05
#set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/ucpu0_logic/ucpu_logic_peq/l2_peq_vld_q_reg_5/CP insertion_delay 0.05
# ignore to port mon*
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_0__wrp0_2326/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_10__wrp0_2325/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_11__wrp0_2324/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_12__wrp0_2323/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_13__wrp0_2322/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_14__wrp0_2321/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_15__wrp0_2320/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_1__wrp0_2319/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_2__wrp0_2318/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_3__wrp0_2317/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_4__wrp0_2316/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_5__wrp0_2315/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_6__wrp0_2314/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_7__wrp0_2313/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_8__wrp0_2312/temp_cto_reg/DB ignore
set_ccopt_property sink_type -pin cpu_subsys_top_Wrapper_inst/cpu_subsys_top_cpu_subsys_sig_mon_o_9__wrp0_2311/temp_cto_reg/DB ignore
# 0330 flatten
# inst_cpu_cluster/inst_cortexa72/ucpu0/uck_cpu/ucpu_main/uck_gclkcx/inst_cbb_clk_gate_dft/inst_cbb_clk_gate/inst_CKLNQCTD12BWP6T16P96CPD/E
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic0/ck_crcx_clk_en_n_dly3_q_reg/CP insertion_delay 0.5
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic0/ck_crcx_clk_en_n_dly2_q_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic1/ck_crcx_clk_en_n_dly3_q_reg/CP insertion_delay 0.5
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic1/ck_crcx_clk_en_n_dly2_q_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic2/ck_crcx_clk_en_n_dly3_q_reg/CP insertion_delay 0.5
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic2/ck_crcx_clk_en_n_dly2_q_reg/CP insertion_delay 0.2
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic3/ck_crcx_clk_en_n_dly3_q_reg/CP insertion_delay 0.5
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic3/ck_crcx_clk_en_n_dly2_q_reg/CP insertion_delay 0.15
#
#inst_cpu_cluster/inst_cortexa72/unoncpu/utm/ucpu_main0/cnthctl_q_reg_0/CP 0.2
#inst_cpu_cluster/inst_cortexa72/unoncpu/utm/ucpu_main0/cntkctl_q_reg_0/CP 0.1
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/l2_cpu0_spr_rd_data_q_reg_60/CP 0.1
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uregs/l2_cpu0_spr_rd_data_q_reg_17/CP 0.1
set_ccopt_property sink_type -pin inst_cpu_crm/inst_pll_test_wrapper/inst_pll_dft_div/pll_div_clk_o_reg_0/CP ignore
# 0402 review
# 15)
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk1/utag_pipe/urrep3/reset3_n_reg/CP insertion_delay 0.25
# 9)
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/ck_l2_tbnk1_clk_en_dly_q_reg/CP insertion_delay -0.1
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_l2/ck_l2_tbnk0_clk_en_dly_q_reg/CP insertion_delay -0.1
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk1/utag_pipe/l2_tbnk_dbnk1_wr_data_l4_q_reg_98/CP insertion_delay -0.05
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk1/utag_pipe/l2_tbnk_dbnk1_wr_data_l4_q_reg_114/CP insertion_delay -0.05
#inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_tbnk1/utag_pipe/l2_tbnk_dbnk1_wr_mask_l4_q_reg_8/CP insertion_delay -0.05
#0406 flatten
set_ccopt_property -pin inst_cpu_crm/CPU_RST_SYNC_2_inst_cpu_rst_fsm_por_rst/resetn_hold_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_crm/CPU_RST_SYNC_2_inst_cpu_rst_fsm_core_rst/resetn_hold_reg/CP insertion_delay 0.15
# 0407 flatten
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic0/urep3/reset3_n_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic1/urep3/reset3_n_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic2/urep3/reset3_n_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/uck_logic/ucpu_logic3/urep3/reset3_n_reg/CP insertion_delay 0.15
set_ccopt_property -pin inst_cpu_cluster/inst_cortexa72/unoncpu/ul2_logic/uarbitration/l2_hwflush_active_q_reg/CP insertion_delay 0.03
|