#floorPlan -su 2 0.5 0.5 0.5 0.5 0.5 ;# -su
floorPlan -d {2450.032 2650 0.52 0.48 0.52 0.48} -fplanOrigin llcorner
#set list_of_points "0.0 1390 1390 820 0 820 0 2350.5 820 2350.5 820 3460.96 3460.96 2245.048 2245.048 0"
#setFPlanMode -enableRectilinearDesign 1
#setObjFPlanPolygon Cell [get_db designs .name] $list_of_points
addObjFPlanCutBox cell [get_db designs .name] 1900 850 2450.032 2650
addHaloToBlock -allMacro 1 1 1 1
#setFinishFPlanMode -activeObj softblkg
#finishFloorplan -fillplaceBlockage soft 20
createPlaceBlockage -type soft -allMacro -outerRingByEdge {5 5 5 5}
#setFPlanMode -rowSitewidth even
#cutRow
#createRouteBlk -name pp -partial 80 -layer all -box [dbGet top.fPlan.box]
#createRouteBlk -name mem -partial 78 -layer all -box {{365 0} {420 1172}}
# assign pin
#setPtnPinStatus -cell [dbget top.name] -pin [dbget top.terms.name *] -status unplaced
setPtnPinStatus -pin [dbget top.terms.name *] -status unplaced
setPinAssignMode -pinEditInBatch true
#setPinConstraint -global -spacing 2 -width 0.038 -depth 0.3 -pinTemplate { M3 F4 F5 D6 D7 D8 D9 D10 D11 D12 }
#setPinConstraint -global -spacing 4 -width 0.036 -depth 0.3 -pinTemplate M3
#setPinConstraint -global -spacing 3 -width 0.038 -depth 0.3 -pinTemplate F5
#setPinConstraint -global -spacing 2 -width 0.038 -depth 0.3 -pinTemplate {D8 D9 D11}
setPinConstraint -global -spacing 2 -width 0.038 -depth 0.3 -pinTemplate { C1 C2 C3 C4 C5 C6 }
#editPin -quiet -use CLOCK -unit TRACK -spacing 4 -pinWidth 0.07 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {D7} -spreadType center -pin "[get_object_name [get_ports -filter "is_clock == true"] ]"
#editPin -quiet -use SIGNAL -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {D11 D9 D7 F5 M3} -pattern fill_track -reverse_alternate -start {800 1140} -end {800 790} -pin $ports_out_name
#editPin -quiet -use SIGNAL -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {D11 D9 D7 F5 M3} -pattern fill_track -reverse_alternate -start {800 780} -end {800 620} -pin [concat [get_object_name $if_port5_out] [get_object_name $if_port5_in]]
#editPin -quiet -use SIGNAL -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {D11 D9 D7 F5 M3} -pattern fill_track -reverse_alternate -start {800 610} -end {800 460} -pin [concat [get_object_name $if_port4_out] [get_object_name $if_port4_in]]
#editPin -quiet -use SIGNAL -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {D11 D9 D7 F5 M3} -pattern fill_track -reverse_alternate -start {800 450} -end {800 300} -pin [concat [get_object_name $if_port1_out] [get_object_name $if_port1_in]]
#editPin -quiet -use SIGNAL -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -side right -layer {M3 F5 D7 D9 D11} -pattern fill_track -reverse_alternate -start {800 290} -end {800 120} -pin $ports_in_name
# 1350.96 2480.825
#editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 2 -layer {C2 C4 C6} -pattern fill_track -start {1350.96 2400} -end {1350.96 1000} -pin "[get_db selected .name]"
#loadIoFile io1.io
set j_port_list_0 ""
set j_port_list_1 ""
set j_port_list_2 ""
set j_port_list_3 ""
set j_port_list_other ""
source -quiet j_get_driver.tcl
set j_pin_connected ""
foreach_in_coll j_obj [get_ports ] {
set j_name [get_db $j_obj .name ]
set j_direction [get_db $j_obj .direction ]
set j 0
if { $j_direction == "out" } {
set j_driver [j_get_driver -port $j_name ]
if { [get_db [get_pins $j_driver ] .obj_type ] == "pin" } {
set j_driver_ref [j_get_driver_ref -port $j_name ]
while { $j < 50 && ([regexp IOBUF $j_driver ] || [regexp BUF $j_driver_ref ] || [regexp INV $j_driver_ref ]) } {
set j_input [j_get_input -pin $j_driver ]
if { [get_pins -leaf -quiet [j_get_driver -pin $j_input ]] == "" && [get_pins -quiet [j_get_driver -pin $j_input ]] != "" } {
set j_driver [get_object_name [get_pins -quiet [j_get_driver -pin $j_input ]]]
break
}
set j_driver [j_get_driver -pin $j_input ]
set j_driver_ref [j_get_driver_ref -pin $j_input ]
incr j
if { [regexp {core_\d} $j_driver ] } { break }
if { ! [regexp BUF $j_driver_ref ] && ! [regexp INV $j_driver_ref ] } { break }
}
}
set j_pin_connected $j_driver
}
if { $j_direction == "in" } {
set j_load [j_get_load -port $j_name ]
if { [get_db [get_pins $j_load ] .obj_type ] == "pin" } {
set j_load_ref [j_get_load_ref -port $j_name ]
while { $j < 50 && ([regexp IOBUF $j_load ] || [regexp BUF $j_load_ref ] || [regexp INV $j_load_ref ]) } {
set j_output [j_get_output -pin $j_load ]
if { [llength [j_get_load -pin $j_output ] ] > 1 } {
set j_load [get_object_name [j_get_load -pin $j_output ]]
break
}
set j_load [j_get_load -pin $j_output ]
if { [get_db [get_pins [j_get_load -pin $j_output ]] .obj_type] == "hpin" } { break }
set j_load_ref [j_get_load_ref -pin $j_output ]
incr j
if { [regexp {core_\d} $j_load ] } { break }
if { ! [regexp BUF $j_load_ref ] && ! [regexp INV $j_load_ref ] } { break }
}
}
set j_pin_connected $j_load
}
switch -regexp $j_pin_connected {
core_0 { lappend j_port_list_0 $j_name }
core_1 { lappend j_port_list_1 $j_name }
core_2 { lappend j_port_list_2 $j_name }
core_3 { lappend j_port_list_3 $j_name }
default { lappend j_port_list_other $j_name }
}
}
set j_port_list_other [get_object_name [get_ports "$j_port_list_other clk" ]]
set j_port_list_other "$j_port_list_other tstop"
set j_port_list_0 [get_object_name [get_ports $j_port_list_0 ]]
set j_port_list_1 [get_object_name [get_ports $j_port_list_1 ]]
set j_port_list_2 [get_object_name [get_ports $j_port_list_2 ]]
set j_port_list_3 [get_object_name [get_ports $j_port_list_3 ]]
set j_port_list_0 "$j_port_list_0 irqo[12] irqo[13] irqo[14] irqo[15] cpurstn[0]"
set j_port_list_1 "$j_port_list_1 irqo[8] irqo[9] irqo[10] irqo[11] cpurstn[1]"
set j_port_list_2 "$j_port_list_2 irqo[4] irqo[5] irqo[6] irqo[7] cpurstn[2]"
set j_port_list_3 "$j_port_list_3 irqo[0] irqo[1] irqo[2] irqo[3] cpurstn[3]"
set j_top_port_list { \
acaddrm_i[0] \
acaddrm_i[10] \
acaddrm_i[11] \
acaddrm_i[12] \
acaddrm_i[13] \
acaddrm_i[14] \
acaddrm_i[15] \
acaddrm_i[16] \
scu_ext_rack_o \
scu_ext_wack_o \
wreadym_i \
}
foreach j_obj $j_top_port_list {
set j_port_list_other [lremove $j_port_list_other $j_obj ]
}
# ports is at side top
set j_width [lindex [get_db designs .bbox] 0 2]
set j_height [lindex [get_db designs .bbox] 0 3]
set j_x $j_width
set j_y $j_height
set j_y_start_1 1930
set j_y_end_1 [expr $j_y_start_1 - 100 ]
set j_y_start_0 1440
set j_y_end_0 [expr $j_y_start_0 - 100 ]
set j_x_start_2 1910
set j_x_end_2 [expr $j_x_start_2 + 100 ]
set j_x_start_3 2100
set j_x_end_3 [expr $j_x_start_3 + 100 ]
set j_y_start_other 1013
set j_y_end_other [expr $j_y_start_other - 162 ]
set j_x_start_top 850
set j_x_end_top [expr $j_x_start_top + 150 ]
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 2 -layer {C2 C4 C6} -pattern fill_track -start "$j_x $j_y_start_other" -end "$j_x $j_y_end_other" -pin $j_port_list_other
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 2 -layer {C2 C4 C6} -pattern fill_track -start "$j_x $j_y_start_1" -end "$j_x $j_y_end_1" -pin $j_port_list_1
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 2 -layer {C2 C4 C6} -pattern fill_track -start "$j_x $j_y_start_0" -end "$j_x $j_y_end_0" -pin $j_port_list_0
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 3 -layer {C1 C3 C5} -pattern fill_track -start "$j_x_start_2 $j_y" -end "$j_x_end_2 $j_y" -pin $j_port_list_2
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 3 -layer {C1 C3 C5} -pattern fill_track -start "$j_x_start_3 $j_y" -end "$j_x_end_3 $j_y" -pin $j_port_list_3
editPin -quiet -use SIGNAL -unit TRACK -spacing 2 -pinDepth 0.3 -fixOverlap 1 -spreadDirection clockwise -edge 1 -layer {C1 C3 C5} -pattern fill_track -start "$j_x_start_top $j_y" -end "$j_x_end_top $j_y" -pin $j_top_port_list
snapFPlan -pin
return
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