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Report : List of Attribute Definitions
Version: Y-2026.03-SP2
Date : Tue Nov 3 17:21:32 2026
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Properties:
A - Application-defined
U - User-defined
I - Importable from design/library (for user-defined)
S - Settable
B - Subscripted
Attribute Name Object Type Properties Constraints
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area cell float A
background_supply_noise cell string A
base_name cell string A
bbox cell string A
bbox_llx cell string A
bbox_lly cell string A
bbox_urx cell string A
bbox_ury cell string A
block_config_name cell string A
block_config_path cell string A
block_mark cell string A
block_timestamp cell string A
bottleneck_cost cell float A
bounding_box cell string A
cell_height cell string A
cell_origin cell string A
cell_rail_dynamic_cswitching cell string A
cell_total_dynamic_cswitching cell string A
cell_width cell string A
cg_clock_gate_level cell int A
cg_clock_tree_level cell int A
cg_downstream_direct_dynamic_network_power cell double A
cg_downstream_direct_dynamic_power cell double A
cg_downstream_direct_hierarchical_cells cell collection A cell
cg_downstream_direct_icg_cells cell collection A cell
cg_downstream_direct_icg_count cell int A
cg_downstream_direct_leaf_cell_count cell int A
cg_downstream_direct_leakage_power cell double A
cg_downstream_direct_reg_cells cell collection A cell
cg_downstream_direct_reg_clock_pin_power cell double A
cg_downstream_direct_reg_count cell int A
cg_downstream_direct_reg_single_bit_eq cell int A
cg_downstream_direct_total_capacitance cell double A
cg_downstream_gated_reg_instances cell int A
cg_incr_efficiency cell double A
clock_pin_power cell double A
critical_path_max cell string A
critical_path_min cell string A
disable_timing cell boolean A
domain cell collection A upf_power_domain
dont_touch cell boolean A,S
drc_violations cell string A
dynamic_power cell double A
early_fall_cell_check_derate_factor cell float A
early_fall_clk_cell_derate_factor cell float A
early_fall_clk_net_delta_derate_factor cell float A
early_fall_clk_net_derate_factor cell float A
early_fall_data_cell_derate_factor cell float A
early_fall_data_net_delta_derate_factor cell float A
early_fall_data_net_derate_factor cell float A
early_rise_cell_check_derate_factor cell float A
early_rise_clk_cell_derate_factor cell float A
early_rise_clk_net_delta_derate_factor cell float A
early_rise_clk_net_derate_factor cell float A
early_rise_data_cell_derate_factor cell float A
early_rise_data_net_delta_derate_factor cell float A
early_rise_data_net_derate_factor cell float A
escaped_full_name cell string A
exact_match_lib_cell_max_fall cell collection A,B lib_cell
exact_match_lib_cell_max_rise cell collection A,B lib_cell
exact_match_lib_cell_min_fall cell collection A,B lib_cell
exact_match_lib_cell_min_rise cell collection A,B lib_cell
exact_match_library cell collection A lib
extra_clock_voltage_margin_early_fall cell float A
extra_clock_voltage_margin_early_rise cell float A
extra_clock_voltage_margin_late_fall cell float A
extra_clock_voltage_margin_late_rise cell float A
full_name cell string A
gate_leakage_power cell double A
glitch_power cell double A
global_coordinate cell string A
has_multi_ground_rails cell boolean A
has_multi_power_rails cell boolean A
has_rail_specific_power_tables cell boolean A
hier_cell_area cell float A
hier_cell_count cell int A
hier_pin_count cell int A
inertial_glitch_power cell double A
internal_power cell double A
internal_power_derate_factor cell float A
intrinsic_leakage_power cell double A
is_active cell boolean A
is_black_box cell boolean A
is_buffer cell string A
is_case_sequential_propagation cell boolean A
is_clock_gating_check cell boolean A
is_clock_network_cell cell boolean A
is_combinational cell boolean A
is_design_mismatch cell boolean A
is_edited cell boolean A
is_fall_edge_triggered cell boolean A
is_fixed cell boolean A,S
is_hierarchical cell boolean A
is_hyperscale_block cell boolean A
is_hyperscale_power_switch_cell cell boolean A
is_ideal cell boolean A
is_integrated_clock_gating_cell cell boolean A
is_interface_logic_model cell boolean U,S
is_macro_switch cell boolean A
is_memory_cell cell boolean A
is_mim_context_reference cell boolean A
is_mux cell boolean A
is_negative_level_sensitive cell boolean A
is_pad_cell cell boolean A
is_positive_level_sensitive cell boolean A
is_power_standby_cell cell boolean A
is_repeater cell boolean A
is_rise_edge_triggered cell boolean A
is_rtl_equivalent cell boolean A
is_rtl_memory cell boolean A
is_sequential cell boolean A
is_three_state cell boolean A
late_fall_cell_check_derate_factor cell float A
late_fall_clk_cell_derate_factor cell float A
late_fall_clk_net_delta_derate_factor cell float A
late_fall_clk_net_derate_factor cell float A
late_fall_data_cell_derate_factor cell float A
late_fall_data_net_delta_derate_factor cell float A
late_fall_data_net_derate_factor cell float A
late_rise_cell_check_derate_factor cell float A
late_rise_clk_cell_derate_factor cell float A
late_rise_clk_net_delta_derate_factor cell float A
late_rise_clk_net_derate_factor cell float A
late_rise_data_cell_derate_factor cell float A
late_rise_data_net_delta_derate_factor cell float A
late_rise_data_net_derate_factor cell float A
leaf_cell_count cell int A
leakage_power cell double A
leakage_power_check cell string A
leakage_power_derate_factor cell float A
lib_cell cell collection A lib_cell
local_coordinate cell string A
macro_width_height cell string A
max_context_leakage_power cell double A
min_context_leakage_power cell double A
number_of_pins cell int A
object_class cell string A
orientation cell string A
original_ref_name cell string A
parasitics_corner_name cell string A
parasitics_operating_temperature cell string A
parasitics_program_name cell string A
parasitics_program_version cell string A
parasitics_tech_file cell string A
parent_cell cell collection A cell
peak_power cell double A
peak_power_end_time cell double A
peak_power_start_time cell double A
pg_pin_info cell collection A pg_pin_info
pin_count cell int A
polygon_shape cell string A
power_cell_type cell string U,S
power_states cell double A
process_max cell float A
process_min cell float A
ref_name cell string A
rtl_ave_reg_dacgee cell double A
rtl_ave_reg_data_aware_gating_efficiency cell double A
rtl_ave_reg_gating_efficiency cell double A
rtl_ave_reg_roade cell double A
rtl_ave_reg_roadf cell double A
rtl_black_box_reason cell string A
rtl_blackbox_total_power cell double A
rtl_cg_buffer_count cell int A
rtl_cg_clock_gate_count cell int A
rtl_cg_clock_gating_efficiency cell float A
rtl_cg_clock_in_freq cell double A
rtl_cg_clock_out_freq cell double A
rtl_cg_fanout_count cell int A
rtl_cg_immediate_reg_ave_q_toggle_rate cell double A
rtl_cg_immediate_reg_count cell int A
rtl_cg_incr_efficiency cell float A
rtl_cg_intrinsic_efficiency cell float A
rtl_cg_inverter_count cell int A
rtl_cg_root_clock_freq cell double A
rtl_cg_total_reg_ave_q_toggle_rate cell double A
rtl_cg_total_reg_count cell int A
rtl_clock_gate_stage cell int A
rtl_clock_network_total_power cell double A
rtl_clock_pin_toggle_rate cell double A
rtl_combo_total_power cell double A
rtl_d_pin_toggle_rate cell double A
rtl_driving_cg_type cell string A
rtl_driving_clock_freq cell double A
rtl_driving_clock_name cell string A
rtl_driving_clock_toggle_rate cell double A
rtl_enable_q_clk_ratio cell double A
rtl_gated_register_ratio cell double A
rtl_hier_name cell string A
rtl_inferred_cg_count cell int A
rtl_instantiated_cg_count cell int A
rtl_mem_d_pin_tr cell double A
rtl_mem_dis_red_toggles cell double A
rtl_mem_disable_cond cell string A
rtl_mem_disable_mod_sp cell double A
rtl_mem_disable_mod_tr cell double A
rtl_mem_disable_sp cell double A
rtl_mem_disable_state_improv_power cell double A
rtl_mem_disable_state_power cell double A
rtl_mem_disable_state_wasted_power cell double A
rtl_mem_disable_tr cell double A
rtl_mem_noacess_cycles_cnt cell double A
rtl_mem_noacess_cycles_cnt_multiport cell double A
rtl_mem_q_pin_tr cell double A
rtl_mem_read_addr_tr cell double A
rtl_mem_read_cond cell string A
rtl_mem_read_cycles_cnt cell double A
rtl_mem_read_mod_sp cell double A
rtl_mem_read_mod_tr cell double A
rtl_mem_read_new_power cell double A
rtl_mem_read_red_toggles cell double A
rtl_mem_read_sp cell double A
rtl_mem_read_stability cell double A
rtl_mem_read_state_improv_power cell double A
rtl_mem_read_state_power cell double A
rtl_mem_read_state_wasted_power cell double A
rtl_mem_read_tr cell double A
rtl_mem_redn_read_cycles_cnt cell double A
rtl_mem_redn_write_cycles_cnt cell double A
rtl_mem_total_cycles_cnt cell double A
rtl_mem_total_cycles_cnt_multiport cell double A
rtl_mem_write_addr_tr cell double A
rtl_mem_write_cond cell string A
rtl_mem_write_cycles_cnt cell double A
rtl_mem_write_mod_sp cell double A
rtl_mem_write_mod_tr cell double A
rtl_mem_write_new_power cell double A
rtl_mem_write_red_toggles cell double A
rtl_mem_write_sp cell double A
rtl_mem_write_stability cell double A
rtl_mem_write_state_improv_power cell double A
rtl_mem_write_state_power cell double A
rtl_mem_write_state_wasted_power cell double A
rtl_mem_write_tr cell double A
rtl_memory_size cell string A
rtl_memory_total_power cell double A
rtl_module_name cell string A
rtl_module_xref cell string A
rtl_q_pin_toggle_rate cell double A
rtl_reg_bus_merged_name cell string A
rtl_reg_bus_merged_width cell int A
rtl_reg_clock_gating_type cell string A
rtl_reg_count_driven_by_cg cell int A
rtl_reg_count_driven_by_inferred_cg cell int A
rtl_reg_count_driven_by_instantiated_cg cell int A
rtl_reg_d_clk_ratio cell double A
rtl_reg_d_q_ratio cell double A
rtl_reg_data_aware_gating_efficiency cell double A
rtl_reg_gating_efficiency cell double A
rtl_reg_m_cg_recommendation cell string A
rtl_reg_m_cg_ungating_reason cell string A
rtl_reg_m_clock_pin_power cell double A
rtl_reg_m_d_clk_ratio cell double A
rtl_reg_m_d_pin_toggle_rate cell double A
rtl_reg_m_d_q_ratio cell double A
rtl_reg_m_dynamic_power cell double A
rtl_reg_m_enable_q_clk_ratio cell double A
rtl_reg_m_gating_efficiency cell double A
rtl_reg_m_internal_power cell double A
rtl_reg_m_is_primary cell boolean A
rtl_reg_m_leakage_power cell double A
rtl_reg_m_q_clk_ratio cell double A
rtl_reg_m_q_pin_toggle_rate cell double A
rtl_reg_m_switching_power cell double A
rtl_reg_m_total_power cell double A
rtl_reg_observability cell double A
rtl_reg_q_clk_ratio cell double A
rtl_reg_rtl_name cell string A
rtl_reg_ungated_reason cell string A
rtl_reg_width cell int A
rtl_register_count cell int A
rtl_register_total_power cell double A
rtl_repeater_clock_network_dynamic_power cell double A
rtl_repeater_comb_dynamic_power cell double A
rtl_source cell string A
rtl_total_cg_count cell int A
rtl_x_coordinate cell double A
rtl_xref cell string A
rtl_y_coordinate cell double A
short_circuit_power cell double A
size_only cell boolean A,S
switching_power cell double A
switching_power_derate_factor cell float A
temperature_max cell float A
temperature_min cell float A
timing_model_type cell string A
total_power cell double A
transport_glitch_power cell double A
upf_isolation_strategy cell string A
upf_retention_strategy cell string A
wire_load_model_max cell string A
wire_load_model_min cell string A
wire_load_selection_group_max cell string A
wire_load_selection_group_min cell string A
x_coordinate_max cell float A
x_coordinate_min cell float A
x_transition_power cell double A
y_coordinate_max cell float A
y_coordinate_min cell float A